Electronic circuit designs are usually stored in memory in computer aided design (CAD) systems in a hierarchical form, or in a flat form. Some CAD tools (e.g., logic optimization, and hierarchical cell simulation tools) typically use or require the hierarchical representation of a circuit design. Tools that modify circuit designs (such as compilers) will leave the hierarchy unchanged so that the user can easily find and check what has been done. Other CAD tools (e.g., timing verification, circuit simulation, and circuit placement and routing tools) typically use or require a flat representation of a circuit design. In a timing verifier, which computes the time required for a signal to go from one interconnection to another through a list of gates and interconnections, the circuit design hierarchy does not carry any useful information.
Increasingly, CAD tools are being linked together (e.g., circuit synthesizers, circuit layout tools, and timing verifiers) and must work on the data structure representations of circuit designs. As a result, there is a need to provide circuit representation data structures that provide both a hierarchical view and a flat view of a circuit design at the same time.